BUSY BUSy BUsy Busy busy....

It seems like ages i din update my blog....sigh....wat to do...i been busy with my digital system assignment....i am so fedd up....dun feel like trying anymore...so tired of it...it is really time consuming...debug debug debug...at the end,there is stil errors!!!! hate it so much...wasted a lot of time there....our lecturer also din really explain much...haihhhh....so tired...every night also sleep at 3 or 4 am....i am becoming a panda soon....arrrrggghhhhhhhhh...here is one part of the codes from my assignments... (i dun wish to continue anymore....sob sob)

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity MetroLRT is port(
clk : in std_logic;
RST : in std_logic;
serial_in_port : in std_logic;
task : in unsigned(1 downto 0);
timeSTP : in std_logic;
stationed : in unsigned(3 downto 0);
addValue : in unsigned(6 downto 0);
serial_out_port : out std_logic;
gate_open_out : out std_logic;
);
end MetroLRT;
architecture rtl of MetroLRT is...............